Researchers at NEC Corporation and Tohoku University have developed the worlds first technology for improving the reliability of spintronics logic integrated circuits. The intention is to reduce the standby power of electronic devices to zero.
Spintronics logic integrated circuits use two of the properties of electrons, namely negative charge and spin, one of the properties of electrons that makes them behave like tiny magnets. By flipping the polarity of these tiny magnets between “north” and “south” according to the direction of an electric current, it is possible to remember the results of a calculation. The behavior of this technology has been verified and proven by using a prototype chip.
The properties has come in to focus as a semiconductor technology, because it has whats called a non-volatility property. This practically means that even if the power is turned off, the properties of the elements will still be retained when the power is turned back on. When used in calculations this in practice means that it can retain data even if the power supply is cut off, because data is remembered using magnetic polarity. It is this non-volatility that has the potential to eliminate the power consumed by electronic devices while they are in standby mode.
The technology use vertical domain wall elements, which have vertical magnetization with respect to a magnetic body. Multiple vertical domain wall elements are loaded for each individual component of a logic integrated circuit. This way there is redundancy concerning what data is remembered. Using this construction enables a high level of reliability to be achieved, because the potential data errors can be detected and corrected. Errors can be caused be by such things as cosmic rays, high and low temperatures, and fluctuations in the write voltage or the write current.that occasionally occur with logic integrated circuits
Key features are according to NEC Corp. and Tohoku University as follows:
- Delivers non-volatile logic integrated circuits with high reliability
Data redundancy is achieved by loading multiple “spin elements” (the elements that remember calculation results until the power is turned back on) for the components of logic integrated circuits. Although the probability of errors occurring with non-volatile logic integrated circuits is very low, errors where calculation result data is remembered incorrectly do occur, and having redundant spin elements enables these errors to be detected and corrected, so that the data can be read correctly. Normally, adding redundant elements would make the physical size of the circuit larger, but vertical domain wall elements can be placed on top of transistor elements and the elements are connected in a series so there is no need for a new transistor to branch the wires. This means high reliability can be achieved without increasing the circuit area.Vertical domain wall elements also feature low electrical resistance on a current pathway, and so by connecting the elements in a series very little extra time or current is required to write data.
- Non-volatile circuits can be designed even without knowledge of spintronics technology
The circuit components that incorporate spin elements support automatic placement and wiring, whereby the placement and wiring of transistors is designed programmatically. This enables non-volatile logic integrated circuits to be designed easily, even without expertise in spintronics.
Spintronics logic integrated circuits can hold data even when the power is turned off, and then recover rapidly when the power is turned back on. There are great expectations for these spintronics logic integrated circuits as a technology capable of significantly reducing power consumption by eliminating the power consumed by electronic devices in standby mode.
These technologies also enable circuits to become highly reliable, which is important for the commercialization of spintronics logic integrated circuits.
NEC Corporation and Tohoku University presented the results at the VLSI Circuit Symposium 2012, an international academic meeting held between Tuesday, June 12 and Saturday, June 16 in Honolulu, Hawaii.